[OS][mini-arm-os] 02-ContextSwitch-1

happy@happy-laptop:/tmp/test/mini-arm-os/02-ContextSwitch-1$ make
arm-none-eabi-gcc -fno-common -ffreestanding -O0 -gdwarf-2 -g3 -Wall -Werror -mcpu=cortex-m3 -mthumb -Wl,-Tos.ld -nostartfiles  os.c startup.c context_switch.S -o os.elf
arm-none-eabi-objcopy -Obinary os.elf os.bin
arm-none-eabi-objdump -S os.elf > os.list

happy@happy-laptop:/tmp/test/mini-arm-os/02-ContextSwitch-1$ make qemu
Press Ctrl-A and then X to exit QEMU

qemu-system-arm -M stm32-p103 -nographic -kernel os.bin
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
LED Off
CLKTREE: HSI Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSI/2 Output Change (SrcClk:HSI InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:HSI InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 8000000 Hz (scale set to 125).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 1000000 Hz (scale set to 1000).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE/128 Output Change (SrcClk:HSE InFreq:8000000 OutFreq:62500 Mul:1 Div:128 Enabled:1)
CLKTREE: HSE/2 Output Change (SrcClk:HSE InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PLLXTPRE Output Change (SrcClk:HSE InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: GPIOA Output Change (SrcClk:PCLK2 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: AFIO Output Change (SrcClk:PCLK2 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: UART2 Output Change (SrcClk:PCLK1 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
OS Starting...
User Task #1